(1) Field of the Invention
The present invention relates generally to semiconductors, and more specifically to a method of forming tungsten (W) interlevel connections (ILC), or "via plugs", between metallized conductive layers in integrated circuit (IC) chips without the detrimental "volcano effect" that causes craterous defects in chips. The method equally applies to "contact plugs" that are deposited over the drain-source-gate regions that form the basis of, for example, MOS (metal-oxide-semiconductor) devices.
(2) Description of the Related Art
Semiconductor devices arrive at their functional state only after having been "personalized" to do specific tasks in a prescribed manner. "Personalization" is achieved through metallization of defined regions in the semiconductor substrate. The process starts first by forming regions of field isolation. Then, in the MOS process, for example, a conductive gate is formed over a dielectric. The source and drain regions are heavily doped. interlevel dielectric layers are deposited over these areas to serve as electrical insulators. Subsequently, holes are opened (e.g., etched) in the interlevel dielectric whereby metal deposited later into these holes form "contact-plugs" which contact the source, drain and gate regions. Depending upon the levels of integration of the IC chip, one or more metal layers with appropriate circuitized patterns or "personalization" are next deposited alternately with interlevel dielectric layers. Connections between the metal layers is provided through "via-plugs." In the highly dense, submicron integrated circuit devices, where small feature sizes are desired, 3 or 4 levels of interconnection metallization may be required.
At the same time that small size features are used to keep the device density as high as possible, the via density is also kept high by stacking the holes one on top of the other as shown in FIG. 1(A). This is more readily possible if the sidewalls of the holes are vertical, for otherwise, with tapered sidewalls, the vias must be staggered as shown in FIG. 1(B). (In both FIGS. 1(A) and 1(B), regions 10, 12, are first and second level metal layers, respectively, and regions 14, 16 are the first and second level insulators, and 18, 20 are the first and second level vias through the respective insulators.) The resulting increase in pattern size results in an area penalty that can significantly decrease packing density. The slug of metal deposited into these vertical holes are referred to as "plugs".
In general, the integrity of the metallization on each level, and in particular, that of the metal plugs--which we distinguish as "contact-plugs" those over the source-gate-drain, and "via-plugs" between the metal layers themselves--in the openings in the interlevel dielectric, is very important in the manufacture of IC chips. When metal is deposited on a surface, what is wanted is a solid, smooth arid continuous interface between the metal surface and the other contacting surface. On the contrary, what is usually found, under certain circumstances, are rugged interfaces with spikes of one material protruding into the other, and vice versa. Traditionally, this "spiking" and metal diffusion into the semiconductor substrate have been the two most encountered problems during metallization. Still another problem that has recently been encountered is the "volcano effect"--which will be described later--stemming from the reaction WF.sub.6 +Ti.fwdarw.TiF.sub.x +by-products in the metallization of tungsten (W) "contact" and "via" plugs.
Usually, barrier layers are used to circumvent the spiking type problems as described in the U.S. Pat. No. 5,232,871: Contact spiking can occur in device fabrication when the device is exposed to high temperatures. It is a phenomenon that is related to solid solubilities. When two dissimilar materials come in contact with each other, there will be an equilibrium concentration of one of the materials into the other material. As an example, when pure silicon and pure aluminum come into contact, the interface at the touching surfaces are initially smooth. During high temperature processing such a an alloy cycle, because aluminum can support larger amounts of silicon, the silicon can move into the metal and leave a void behind. Conversely, the metal may diffuse through a heavily doped junction and cause increased leakage current or a short circuit to the substrate. The result of both processes (silicon going to the aluminum and aluminum going into the silicon) is an aluminum-silicon interface that is not smooth, but spiky. The process is referred to as spiking. Ideally, barrier layers keep spiking and dissolution of one material into another from occurring. In reality, that may not be the case.
Spiking and metal diffusion mechanisms may be minimized by using silicon containing aluminum alloys such as Al-1%Si or using barrier materials such as titanium-tungsten (Ti-W). In fact, sputtered titanium nitride (TiN) is used as a barrier layer. However, TiN has problems of its own. Firstly, as it is being sputtered on a surface in a sputtering chamber, it forms itself as columnar structures with gaps in between the columns. The gaps are referred to as grain boundaries, and during metallization, they allow metal to migrate through them to reach the underlying surface. If the underlying surface is the substrate, then spike formation and metal diffusion can occur into the drain-source-gate regions, which as mentioned before, are not desirable.
There are a number of solutions that are proposed in prior art to solve the spiking and diffusion problems. In one metallization process, an attempt is made to fill the gaps in between the columns, or the grain boundaries in the TiN barrier by "stuffing" them with oxygen (O.sub.2) gas molecules ("stuffed barriers" are discussed in the book "Silicon Processing for the VLSI Era" by S. Wolf, Lattice Press, Sunset Beach, Calif., 1990, Vol. 2, p. 123) prior to the deposition of the metal so that the metal would not be able to pass by these molecules and migrate to the underlying substrate. However, it is found that this "oxygen stuffing" is not very effective when done at atmospheric room temperature because the gas adsorption process then is neither adequate nor reliable. Another proposal goes one step further where a atmospheric but high temperature process or plasma enhanced reaction process is used. Still the results are not totally effective. (U.S. Pat. No. 5,232,871).
Still another prior art employs still higher temperatures to improve the TiN integrity. As stated in U.S. Pat. No. 5,232,871, after the substrate has been first coated with TiN, the substrate is processed in a Rapid Thermal Annealer (RTA) at about 600.degree. C. to 800.degree. C. in nitrogen for 30 to 90 seconds. The high temperature causes the reaction of nitride and nitrogen to form significantly more TiN than when exposed to atmospheric air at room temperature. The barrier layer becomes sealed preventing spike formation or metal diffusion into the substrate. Subsequently, metals may be deposited without having to worry about the integrity of the barrier layer. Unfortunately, RTA's, while solving one set of problems, introduce another set of problems down-stream the production line. One serious problem is the warping of the substrates caused by high temperatures and the resulting high temperature gradients thereof that can be imposed on the surface of the substrates unless the equipment is adjusted frequently. If the substrate is warped, lithographic patterns cannot be aligned over the entire surface of the substrate which is an essential operation in the manufacture of IC devices. Furthermore, RTA's cannot be used after metal processing since the metal will melt and lines will short. Additionally, RTA's have been plagued by numerous equipment failures, and are usually limited in their use as research tools.
As seen above, the prior art has been focused on trying to seal the grain boundaries--that is, the spaces between the columnar structures of the barrier layer--so as to be able to stop the migration of the subsequently deposited metal into those spaces as a measure to prevent the spiking and metal diffusion problems at the interfaces. There is an additional problem which the prior art does not address. That is the problem of the "volcano effect".
Volcano effect is caused by the eruption of certain substances that have entered into the grain boundaries of the barrier layer during metallization. These substances may be process contaminants, etchant compounds harbored in the sidewalls of the holes in the interlevel dielectric, or other by-products of the metallization process. In the tungsten metallization, the following reaction takes place: EQU WF.sub.6 +Ti.fwdarw.TiF.sub.x +by-products, namely,
the tungsten fluoride (WF.sub.6) reacts with the titanium (Ti) film layer to yield titanium fluoride (TiFx) plus some other by-products. It is the titanium fluoride (TiFx)--which can easily slip by even if the grain boundaries have been "stuffed" with oxygen molecules--that erupt during metallization and result in craterous defects as seen on a substrate shown in FIG. 2A in the magnified plan view of one of the circular vias under a rectangularly shaped pad is also shown in FIG. 2B.